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Actel has an allocated Vendor ID that CorePCIF customers may use, and Actel will allocate a unique Device ID when
the Actel Vendor ID is used. Actel will allocate unique subsystem Vendor IDs on request. Contact Actel Technical
Support (tech@actel.com ) for more information.
The capability pointer is used to point to the CorePCIF vendor capability data, and also to the hot-swap capability, if
enabled. The capability list structure varies, depending on the core configuration.
Read/Write Configuration Registers
The following registers have at least one bit that is both read- and write-capable. For a complete description, refer to the
appropriate table.
? Command Register (04h) ( Table 7-6 )
? Status Register (06h) ( Table 7-7 on page 109 )
? Memory Base Address Register Bit Definition ( Table 7-8 on page 109 )
? I/O Base Address Register Bit Definition ( Table 7-9 on page 110 )
? Interrupt Register (3Ch) ( Table 7-10 on page 110 )
? Interrupt Control/Status Register (48h) ( Table 7-11 on page 110 )
Optional Hot-Swap Register (80h) ( Table 7-12 on page 110 )
Table 7-6 · Command Register 04 Hex
Bit(s)
0
1
2
3
4
5
6
7
8
9
10
15:11
108
Type
RW
RW
RW
RO
RO
RO
RW
RO
RW
RO
RW
RO
Description
I/O Space
A value of 0 disables the device's response to I/O space addresses. Set to 0 after reset.
Memory Space
A value of 0 disables the device's response to memory space addresses. Set to 0 after reset.
Bus Master
When set to 1, this bit enables the macro to behave as a PCI bus Master. For Target-only implementation, this bit is
read-only and is set to 0.
Special Cycles
Response to special cycles is not supported in the core. Set to 0.
Memory Write and Invalidate Enable
Memory Write and Invalidate Enable is not supported by the core. Set to 0.
VGA Palette Snoop
Assumes a non-VGA peripheral. Set to 0.
Parity Error Response
When 0, the device ignores parity errors. When 1, normal parity checking is performed. Set to 0 after reset.
Wait Cycle Control
No data-stepping supported. Set to 0.
SERRN Enable
When 0, the SERRN driver is disabled. Set to 0 after reset.
Set to 0. Only fast back-to-back transactions to the same agent are allowed.
Interrupt Disable
When set, this prevents the core from asserting its INTAn output. This bit is set to 0 after reset.
Reserved. Set to '00000'.
v4.0
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